Host-computing systems, such as personal computers, are often operated as nodes on a communications network, where each node is capable of receiving data from the network and transmitting data to the network. Data is transferred over a network in groups or segments, wherein the organization and segmentation of data are dictated by a network operating system protocol. Many different protocols exist, and data segments which correspond to different protocols may even co-exist on the same communications network. In order for a node to receive and transmit information packets, the node is equipped with a peripheral network interface controller, which is responsible for transferring information between the communications network and the host system. For transmission, the host processor constructs data or information packets in accordance with a network operating system protocol and passes them to the network peripheral. In reception, the host processor retrieves and decodes packets received by the network peripheral. The host processor performs many of its transmission and reception functions in response to instructions from an interrupt service routine associated with the network peripheral. When a received packet requires processing, an interrupt may be issued to the host system by the network peripheral. The interrupt has traditionally been issued after either all of the bytes in a packet or some fixed number of bytes in the packet have been received by the network peripheral.
Many computer systems include a peripheral bus, such as a peripheral component interconnect (PCI or PCI-X) bus for exchanging data between the host processor and high throughput devices, such as memory, network interfaces, display, and disk drives. The host processor and memory can be directly or indirectly connected to the PCI bus along with other devices, such as graphic display adapters, disk controllers, sound cards, etc., where such devices may be coupled directly or indirectly (e.g., through a host bridge) to the PCI or PCI-X bus. In other configurations, the peripheral systems and the main host system memory are connected to the PCI-X bus, wherein a peripheral system may operate as PCI-X bus master capable of direct memory access (DMA) operations to transfer data to and from the host memory. The host processor typically interacts with the PCI-X bus and main host system memory via a memory controller, and the host system may further include a cache memory for use by the host processor.
The PCI-X host bus architecture provides several performance advantages over conventional PCI systems, such as increased operating frequency (e.g., 33 to 133 MHz) and improved maximum peak bandwidth. One important performance enhancing feature of the PCI-X architecture is the addition of split transactions, which may be used in transferring data across the PCI-X host bus between the host and the network controller. Split transactions replace the delayed transactions of PCI architectures, in which the target device terminated the transfer with a retry and fetches the data from memory. The initiator then retried the transaction at a later time, and the target would then hopefully complete the transfer if the data was then ready. These PCI delayed transactions essentially forced the transaction initiator to repeatedly retry the transaction until the target obtained the data, resulting in significantly reduced system bandwidth. However, conventional network controllers designed for PCI operation do not support this type of split transaction, and accordingly cannot realize all the performance advantages of the PCI-X standard increase system throughput. Accordingly, there remains a need for improved data transfer methods and systems to facilitate improved performance in transferring data between a host computer and a network controller.